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TECHNICAL DATA
KK74ACT192
Presettable BCD/Decade UP/DOWN Counter
High-Speed Silicon-Gate CMOS
The KK74ACT192 is identical in pinout to the LS/ALS192, HC/HCT192. The KK74ACT192 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. This counter may be preset by entering the desired data on the P0, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.Both a Terminal Count Down (TCD) and Terminal Count Up (TCU) Outputs are provided to enable cascading of both up and down counting functions. The TCD output produces a negative going pulse when the counter underflows and TCU outputs a pulse when the counter overflows. The counter can be cascaded by connecting the TCU and TCD outputs of one device to the Count Up Clock and Count Down Clock inputs, respectively, of the next device. * TTL/NMOS Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A; 0.1 A @ 25C * Outputs Source/Sink 24 mA
ORDERING INFORMATION KK74ACT192N Plastic KK74ACT192D SOIC TA = -40 to 85 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC PIN 8 = GND
1
KK74ACT192
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs)
*
Min 4.5 0 -40
Max 5.5 VCC 140 +85 -24 24
Unit V V C C mA mA ns/V
VCC =4.5 V VCC =5.5 V
0 0
10 8.0
VIN from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
2
KK74ACT192
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH VIL VOH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Test Conditions VOUT=0.1 V or VCC-0.1 V VOUT=0.1 V or VCC-0.1 V IOUT -50 A VIN=VIH or VIL IOH=-24 mA IOH=-24 mA VOL Maximum LowLevel Output Voltage IOUT 50 A
* *
Guaranteed Limits 25 C 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 -40C to 85C 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 75 -75 8.0 80 A mA mA A V Unit V V V
V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 5.5 5.5 5.5 5.5
VIN=VIH IOL=24 mA IOL=24 mA
IIN IOLD IOHD ICC
Maximum Input Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package)
VIN=VCC or GND VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND
*
All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time.
FUNCTION TABLE
Inputs CPU X X Mode CPD X X H H Reset(Asyn.) Preset(Asyn.) No Count Count Up Count Down No Count The KK74ACT192 can be preset to any state, but will not count beyond 9. If preset to state 10, 11, 12, 13, 14 or 15, it will follow the sequence 10, 11, 6: 12, 13, 4: 14, 15, 2 if counting Up, and follow the sequence 15, 14, 13, 12, 11, 10, 9 if counting Down. Logic equations For Terminal Count: TCU = Q0 * Q3 * CPU TCD = Q0 * Q1 * Q2 * Q3 * CPD
MR
PL
H X L L L H L H L H L H X = don't care
H H
3
KK74ACT192
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits Symbol Parameter 25 C Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPLH tPHL CIN Maximum Clock Frequency (Figure 1) Propagation Delay, CPU or CPD to TCU or TCD (Figure 2) Propagation Delay, CPU or CPD to TCU or TCD (Figure 2) Propagation Delay, CPU or CPD to Qn (Figure 1) Propagation Delay, CPU or CPD to Qn (Figure 1) Propagation Delay, Pn to Qn (Figure 3) Propagation Delay, Pn to Qn (Figure 3) Propagation Delay, PL to Qn (Figure 4) Propagation Delay, PL to Qn (Figure 4) Propagation Delay, MR to Qn (Figure 5) Propagation Delay, MR to TCU (Figure 6) Propagation Delay, MR to TCD (Figure 6) Propagation Delay, PL to TCU or TCD (Figure 6) Propagation Delay, PL to TCU or TCD (Figure 6) Propagation Delay, Pn to TCU or TCD (Figure 6) Propagation Delay, Pn to TCU or TCD (Figure 6) Maximum Input Capacitance 4.5 100 15 14 12 12 12 12 12 15 15 14 14 15 11 15 15 4.5 Max -40C to 85C Min 80 16.5 15.5 13.5 13.5 13.5 13.5 13.5 16.5 16.5 15.5 15.5 16.5 12.5 16.5 16.5 Max MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF Unit
Typical @25C,VCC=5.0 V CPD Power Dissipation Capacitance 45 pF
4
KK74ACT192
TIMING REQUIREMENTS (CL=50pF, Input tr=tf=3.0 ns, VCC=5.0 V 10%)
Guaranteed Limits Symbol tsu th tw tw tw trec trec Parameter Minimum Setup Time, Pn to PL (Figure 7) Minimum Hold Time, PL to Pn (Figure 7) Minimum Pulse Width, PL (Figure 4) Minimum Pulse Width, CPU or CPD (Figure 1) Minimum Pulse Width, MR (Figure 5) Minimum Recovery Time, PL to CPU or CPD (Figure 5) Minimum Recovery Time, MR to CPU or CPD (Figure 5) 25 C 8 -1.0 14 10 12 8 14 -40C to 85C 9 -1.0 15 11 14 9 16 Unit ns ns ns ns ns ns ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
5
KK74ACT192
Figure 5. Switching Waveforms
Figure 6. Switching Waveforms
Figure 7. Switching Waveforms
TIMING DIAGRAM
6
KK74ACT192
EXPANDED LOGIC DIAGRAM
7
KK74ACT192
N SUFFIX PLASTIC DIP (MS - 001BB)
A
Dimension, mm
16 9 B
Symbol A
MIN 18.67 6.1
MAX 19.69 7.11 5.33
1
8
B C
F L
D F
0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38
0.56 1.78
C -T- SEATING
PLANE
G H
H J
N G D 0.25 (0.010) M T K M
J K L M N
10 3.81 8.26 0.36
NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC (MS - 012AC) Dimension, mm
A 16 9
Symbol A
MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0 0.1 0.19 5.8 0.25
MAX 10 4 1.75 0.51 1.27
H
B
P
B C
1
G
8 C R x 45
D F G
-TD 0.25 (0.010) M T C M K
SEATING PLANE
J
F
M
H J K M P R
8 0.25 0.25 6.2 0.5
NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side.
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